Compact device modeling for established and emerging technologies with the Qucs GPL circuit simulator

Current trends in circuit simulation technology suggest a strong movement towards software packages which promote equation-defined compact semiconductor device modeling and circuit macromodeling. Today, the Verilog-A subset of the Verilog-AMS hardware description language is one of the most popular choices of hardware description language for model construction. The ldquoQuite universal circuit simulatorrdquo (Qucs) is a GPL software package supporting the MOS-AK Verilog-A standardization initiative. This paper outlines how equation centered modeling can act as a strong support vehicle for the construction of new device models and circuit macromodels. The material presented in the text explores the relationship between device model specifications, equation-defined devices and Verilog-A code generation. A number of examples demonstrate the capabilities of the model construction tools implemented by the Qucs development team.