A novel BIST scheme for low power testing

A novel BIST structure is presented which can greatly reduce the test power dissipation without losing fault coverage. Single input change test pattern is generated by a counter and a gray encoder. The built-in test vectors are generated by the single input change patterns which are exclusive-ORed with seeds generated by the modified LFSR. All test vectors will be single input change patterns during 2^m test clock period. Thus the switching activities of test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test power and low hardware overhead. Experiments conducted on ISCAS´89 benchmark circuits demonstrate that proposed scheme gives better fault coverage with a large reduction in power dissipation during testing.