A new test data compression method for system-on-a-chip

This paper presents a new test data compression method which simultaneously reduces test data volume, test application time and test power for system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length code and the decompression architecture is also presented. For data streams that are composed of both runs of 0´s and runs of 1´s, alternating run-length codes can be used to reduce the test data volume. The don´t care bit will be set to 0 or 1 according to the input data stream. Experimental results for ISCAS´89 benchmark circuits show that greatly reduced test data volume, test application time and scan shifting power in all cases.