Influences of elevated extension structure on the performance of MISFETs with high-K gate dielectrics

Influences of the elevation of the source/drain extension on the performance of MISFETs with high-K gate dielectrics have been investigated using a device simulation. The phenomena related to high-K gate dielectrics, such as FIBL, ZIBL and FIBS, are enhanced with the extension elevation. However, the enhancement is negligible with the presence of thin low-K sidewalls. The parasitic capacitance between the gate and the source/drain extension increases with increasing extension elevation. However, it is smaller than that of the device with SiO/sub 2/ gate dielectric because distances between the gate and elevated extensions are large in case of high-K gate dielectrics. Consequently, a shorter propagation delay time of CMOS inverter (t/sub pd/) can be expected with the high-K gate dielectric and the elevated extension.