Title :
A high-performance area-efficient AES cipher on a many-core platform
Author :
Liu, Bin ; Baas, Bevan M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA
Abstract :
This paper presents the design and software implementation of a high-performance area-efficient Advanced Encryption Standard (AES) cipher on a many-core platform. A preliminary cipher design is partitioned and mapped to an array of 70 small processors, and offers a throughput of 16.625 clock cycles per byte. The usage of instruction and data memory, and the workload of each processor are characterized for further optimization. Through workload balancing and processor fusion, the throughput of the cipher is increased by 43% to 9.5 clock cycles per byte, while the number of processors utilized is reduced to 59, which is only 10.03 mm2 in a 65 nm fine-grained many-core system. In comparison with published AES implementations on general purpose processors, our design has 3.6-10.7 times higher throughput per area. Moreover, the presented design shows 1.5 times higher throughput than the TI DSP C6201 and 3.4 times higher throughput per area than the GeForce 8800 GTX.
Keywords :
clocks; cryptography; microprocessor chips; multiprocessing systems; parallel processing; resource allocation; GeForce 8800 GTX; TI DSP C6201; clock cycles; data memory; fine-grained many-core system; high performance area-efficient AES cipher; high-performance area-efficient advanced encryption standard cipher; instruction memory; processor fusion; processor workload; size 65 nm; workload balancing; Arrays; Clocks; Digital signal processing; Encryption; Program processors; Throughput; Advanced Encryption Standard (AES); Asynchronous Array of Simple Processors (AsAP); many-core processor; parallel mapping;
Conference_Titel :
Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
978-1-4673-0321-7
DOI :
10.1109/ACSSC.2011.6190389
