DocumentCode
1936810
Title
Pipeline control for a single cycle VLSI implementation of a complex instruction set computer
Author
Stiles, D.R. ; McFarland, H.L.
Author_Institution
NexGen Microsyst., San Jose, CA, USA
fYear
1989
fDate
Feb. 27 1989-March 3 1989
Firstpage
504
Lastpage
508
Abstract
A description is given of the pipeline control techniques used in the NexGen processor. This processor implements a complex-instruction-set architecture which supports OS/2 applications. The processor achieves single-cycle execution of most instructions, and has numerous hardware accelerators which minimize pipeline penalties and reduce cycle counts for complex instructions.<>
Keywords
VLSI; computer architecture; instruction sets; OS/2; complex instruction set computer; hardware accelerators; pipeline control; single cycle VLSI implementation; single-cycle execution; Application software; Computer aided instruction; Computer architecture; Decoding; Hardware; Pipelines; Protocols; Read-write memory; Technical Activities Guide -TAG; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-1909-0
Type
conf
DOI
10.1109/CMPCON.1989.301984
Filename
301984
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