Scalable coherent interface

The scalable coherent interface (SCI) project (formerly known as SuperBus) is based on experience gained during the development of Fastbus (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 Gb/s per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters, and general switched interconnections like Banyon, Omega, or full crossbars. SCI abandons the immediate handshake characteristics of the present generation of buses in favor of a packet-based protocol. SCI avoids wire-ORs, broadcasts, and even ordinary passive bus structures, except that a lower-performance (1 Gb/s per backplane instead of per processor) implementation using a register insertion ring architecture on a passive backplane appears to be possible using the same interface as for the more costly switch networks. A summary is presented of current directions, and the status of the work in progress is reported.<>