Title :
Scalable I/O architecture for buses
Author_Institution :
Apple Comput., Cupertino, CA, USA
fDate :
Feb. 27 1989-March 3 1989
Abstract :
The author discusses current IEEE activities on the P1394 bus standard (1 Mb/s) and the P1596 interconnect (1 Gb/s), which concern the definition of standard control register locations, formats, and functions. This scalable definition, called an I/O architecture, is being considered for use by other bus standards as well (P896.1 Futurebus and the P1014 VME bus standards). The scalable I/O architecture definition is bus-technology-independent, and supports large multiple-bus configurations. Several of the scalable features of the I/O architecture are described.<>
Keywords :
computer interfaces; standards; 1 Gbit/s; 1 Mbit/s; IEEE activities; P1014 VME bus standards; P1394 bus standard; P1596 interconnect; P896.1 Futurebus; buses; formats; multiple-bus configurations; scalable I/O architecture; standard control register locations; Backplanes; Computer architecture; Costs; IEEE activities; Integrated circuit interconnections; Multiprocessing systems; Registers; Scalability; Standards development; Switches;
Conference_Titel :
COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-1909-0
DOI :
10.1109/CMPCON.1989.301990
