MediaSoC: a system-on-chip architecture for multimedia application

Author

Liu, Peng ; Wang, Wei-dong ; Xiao, Zhi-bin ; Lai, Li-ya ; Teng, Zhao-wei ; Yu, Guo-jun ; Ying-biao Yao ; Chen, Ke-ming ; Jiang, Zhi-di ; Zhang, Yi-xiong ; Zhou, Jian ; Wei-guang Cai ; Zhai, Zhi-bo ; Shi, Ce ; Yao, Qing-dong

Author_Institution

Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China

fYear

2005

fDate

28-30 May 2005

Firstpage

161

Lastpage

164

Abstract

The MediaSoC322IA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with tie processor cores. The MediaSoC3221A is fabricated in a 0.18μm 6LM standard-cell SMIC CMOS technology, occupies about 20 mm², and operates at 180 MHz. The MeidaSoC3221A are used to audio/video decoder for embedded multimedia application.

Keywords

CMOS digital integrated circuits; data compression; multimedia systems; system-on-chip; video coding; 0.18 mum; 180 MHz; CMOS technology; MediaSoC; bit stream processing; digital video encoder; multimedia application; multimedia processing; programmable processor core; system-on-chip architecture; Auditory displays; CMOS technology; Digital signal processing; Multimedia systems; Process control; Random access memory; Reduced instruction set computing; SDRAM; Streaming media; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on

Print_ISBN

0-7803-9005-9

Type

conf

DOI

10.1109/IWVDVT.2005.1504576

Filename

1504576