Combining parallel lifting and retiming architecture for discrete wavelet transform

The implementation based on lifting scheme of discrete wavelet transform has great advantages compared with that based on convolution. However, the critical path of the conventional lifting algorithm based implementation is potentially longer than that of convolution-based implementation. In this paper, an improved lifting algorithm for the wavelet filters and its VLSI architecture are presented, in which parallelism of arithmetic operations in each lifting step is exploited, and a retiming technique is employed to optimize design. Compared with the other works reported in previous literature, the proposed architecture is a more efficient alternative in reducing critical path and hardware cost.