A new fast algorithm for 8×8 2-D DCT and its VLSI implementation

Author

Tian, Mao ; Li, Guang-Jun ; Peng, Qi-Zong

Author_Institution

Univ. of Electron. Sci. And Technol. of China, Sichuan, China

fYear

2005

fDate

28-30 May 2005

Firstpage

179

Lastpage

182

Abstract

Due to the importance of the discrete cosine transform (DCT) in the field of transform coding of images, various algorithms and architectures for real-time 2-D DCT processor designs have been proposed. In this paper we present a new fast algorithm for 8×8 2-D DCT based on partial sum and its corresponding hardware architecture for VLSI realization. The algorithm costs fewest multipliers in theory and the system is a serial-in serial-out system. Theoretical proof and simulation results on FPGA devices show the efficiency of the algorithm. The kernel architecture corresponding to the algorithm is regular with lower complexity and performs high throughput.

Keywords

VLSI; discrete cosine transforms; field programmable gate arrays; image coding; transform coding; 8×8 2D DCT; FPGA device; VLSI architecture; VLSI implementation; discrete cosine transform; fast algorithm; image coding; kernel architecture; serial-in serial-out system; Algorithm design and analysis; Costs; Discrete cosine transforms; Field programmable gate arrays; Hardware; Kernel; Process design; Throughput; Transform coding; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on

Print_ISBN

0-7803-9005-9

Type

conf

DOI

10.1109/IWVDVT.2005.1504580

Filename

1504580