• DocumentCode
    1937248
  • Title

    A fast four-via multilayer MCM router

  • Author

    Khoo, Kei-Yong ; Cong, Jason

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
  • fYear
    1993
  • fDate
    15-18 Mar 1993
  • Firstpage
    179
  • Lastpage
    184
  • Abstract
    An efficient multilayer general area router, named V4, for MCM and dense PCB designs is presented. The unique feature of the V4 router is that it uses no more than four vias to route every net and yet produces high quality routing solutions. A number of combinatorial optimization techniques are used in the router to produce high quality routing solutions in polynomial time. As a result, it is independent of net ordering, runs much faster, and has far less memory requirement compared to other multilayer general area routers. The router was tested on several examples, including two industrial MCM designs. Compared with the 3-D maze router, on average the V4 router uses 2% less wire length, 31% fewer vias, and runs 26 times faster. Compared with the SLICE router, on average the V4 router uses 4% less wire length and runs 4.6 times faster
  • Keywords
    circuit layout CAD; multichip modules; network routing; printed circuit design; 3D maze router; SLICE router; V4 router; combinatorial optimization techniques; dense PCB designs; four-via multilayer MCM router; general area router; industrial MCM designs; net ordering; polynomial time; wire length; Algorithm design and analysis; Computer science; Nonhomogeneous media; Polynomials; Propagation losses; Reflection; Routing; Signal design; Testing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multi-Chip Module Conference, 1993. MCMC-93, Proceedings., 1993 IEEE
  • Conference_Location
    Santa Cruz, CA
  • Print_ISBN
    0-8186-3540-1
  • Type

    conf

  • DOI
    10.1109/MCMC.1993.302130
  • Filename
    302130