Novel low power Class-B output buffer

Author

Yu, Pang-Cheng ; Wu, Jiin-Chuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

6

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

633

Abstract

This paper describes the design of a Class-B output buffer for driving large capacitance load in flat panel display. Due to the large number of output buffers on a column driver chip, the quiescent current of the output buffer must be reduced. A comparator which produces full-swing output is used in the negative feedback path to eliminate quiescent current in the last stage. The proposed circuit was implemented in a 0.8 μm CMOS process. The measured maximum static current is 54 μA. With 5 V supply voltage and 600 pF load, the tracking error voltage is less than ±8 mV and the output swing is from 0.5 V to 5 V. The settling time for 4 V swing to 0.2% is 8 μs, which is more than adequate for driving 1204*1280 pixels LCD panel with 86 Hz frame rate

Keywords

CMOS analogue integrated circuits; buffer circuits; circuit feedback; comparators (circuits); driver circuits; flat panel displays; liquid crystal displays; 0.5 to 5 V; 0.8 micron; 1204 pixel; 1280 pixel; 1541120 pixel; 5 V; 54 muA; 600 pF; 8 mus; 86 Hz; CMOS process; Class-B output buffer; LCD panel; column driver chip; comparator; flat panel display; frame rate; full-swing output; large capacitance load; maximum static current; negative feedback path; output swing; quiescent current; settling time; tracking error voltage; Buildings; Capacitance; Circuits; Design engineering; Differential amplifiers; Flat panel displays; Liquid crystal displays; Power engineering and energy; Pulse inverters; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.705434

Filename

705434