Title :
A VLSI residue arithmetic multiplier with fault detection capability
Author :
Bobin, V. ; Radhakrishnan, D.
Author_Institution :
Dept. of Electr. Eng., Idaho Univ., Moscow, ID, USA
Abstract :
A programmable residue-arithmetic-based multiplier is presented. The modulo-m multipliers are implemented using a set of identical multiplexer modules designed in pass logic. This makes the design simple, easily expandable, and ideally suited for VLSI implementation. The multiplier has single residue fault detection capability
Keywords :
MOS integrated circuits; VLSI; digital arithmetic; fault location; integrated logic circuits; multiplying circuits; MOS IC; RNS; VLSI implementation; modulo-m multipliers; pass logic; programmable residue-arithmetic-based multiplier; residue number system; set of identical multiplexer modules; single residue fault detection capability; Complexity theory; Digital arithmetic; Electrical fault detection; Fault detection; Fault tolerance; Integrated circuit interconnections; Multiplexing; Signal design; Signal processing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63385
