Common-mode voltage reduction with two-phase modulation in three-level PWM inverter

It is necessary for an inverter system to eliminate high-frequency leakage currents through parasitic capacitances of switches and loads to the ground from the EMC point of view. A new two-phase modulation method for reduction of common-mode voltages in a three-level three-phase PWM inverter is proposed. The principle is to eliminate the common-mode voltage simply by limiting combinations of the output phase voltage levels of the three-level inverter. A new space vector generation and deadtime correction techniques based on a new two-phase modulation method are proposed to reduce both common-mode voltages and switching losses. Then it is investigated by experiment. The proposed method is compared with the conventional methods and is validated for its effectiveness.