Hardware efficient FIR filter structures from linear program design constraints

Hardware efficient structures for high decimation filters have received much attention due to the explosion in digital communications. However, they do not address wideband digital receiver applications that require processing channels as wide as the input bandwidth. Digital filters that offer decimation ranges from 1 to 64 present a hardware design challenge. This paper presents a novel filter design technique that generates FIR structures with no multipliers. The design process exploits linear programming techniques to constrain the filter coefficients during the optimization process. The technique has been applied to the design of a single-chip sub-band tuner that can continuously process a 100 Msps (40 MHz bandwidth) input data rate