• DocumentCode
    1937869
  • Title

    Proceedings Seventh IEEE International High-Level Design Validation and Test Workshop

  • fYear
    2002
  • fDate
    29-29 Oct. 2002
  • Keywords
    design for testability; formal verification; logic testing; microprocessor chips; program debugging; RTL verification; debugging; design for testability; formal verification methods; global system validation; high level design validation; processor validation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International
  • Conference_Location
    Cannes, France
  • Print_ISBN
    0-7803-7655-2
  • Type

    conf

  • DOI
    10.1109/HLDVT.2002.1224418
  • Filename
    1224418
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1937869