• DocumentCode
    1937912
  • Title

    Multiple-valued-input TANT networks

  • Author

    Perkowski, Marek A. ; Chrzanowska-Jeske, Malgorzata

  • Author_Institution
    Dept. of Electr. Eng., Portland State Univ., OR, USA
  • fYear
    1994
  • fDate
    25-27 May 1994
  • Firstpage
    334
  • Lastpage
    341
  • Abstract
    The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a four-level binary network with input decoders which realize multiple-valued literals. Similar to mvPLAs, mvTANTs have regular structures with predictable timing. Compared with mvPLAs, however, they have at least 25% less input wires to the third-level (NAND) plane and not more outputs from the second-level (AND) plane than the mvPLA. Thus, in many cases they have less gates and connections, and are useful to minimize Boolean functions in cellular FPGAs and other regular structures
  • Keywords
    Boolean functions; logic arrays; many-valued logics; Boolean functions minimisation; binary outputs; cellular FPGAs; four-level binary network; input decoders; multiple-valued inputs; multiple-valued literals; multiple-valued-input TANT networks; mvPLAs; mvTANTs; regular structures; three-level networks; Algebra; Boolean functions; Circuit synthesis; Decoding; Field programmable gate arrays; Logic devices; Minimization; Programmable logic arrays; Programmable logic devices; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on
  • Conference_Location
    Boston, MA
  • Print_ISBN
    0-8186-5650-6
  • Type

    conf

  • DOI
    10.1109/ISMVL.1994.302181
  • Filename
    302181