A mixed-level MOS logic simulator utilizing a new continuous strength algebra (CSAL)

A new evaluation method for logical MOS gates is presented. The approach is suitable for mixed-level simulation of gates and switches. A logical MOS gate models a driver-load transistor network, performing a Boolean logic function, in a static manner. The gate is normally represented by a Boolean expression, of which conventional evaluations at the gate level provide the signal level but not the signal strength of the gate output. In order to overcome this limitation, a new expression (compatible with the Boolean expression) is defined over a new continuous strength algebra (CSAL), and it is then evaluated to provide the signal level and strength for the gate output. This approach achieves gate-level computation speed by using the higher level of abstraction and switch-level accuracy by utilizing the new algebra