Title :
Complete test set for multiple-valued logic networks
Author :
Wang, Hui Min ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A complete test set (CTS) is defined and derived for multiple-valued logic (MVL) Min/Max networks. The CTS can detect any single and multiple stuck-at faults of the MVL Min/Max network regardless of its implementation. Two splitting algorithms to generate the CTS or a given MVL function are proposed. One algorithm demonstrates over 2 orders speed improvement and 3 orders memory savings and the other algorithm demonstrates over 4 orders speed improvement and 2 orders memory savings with respect to the conventional truth table enumerating method
Keywords :
fault location; logic testing; many-valued logics; complete test set; memory savings; multiple-valued logic networks; splitting algorithms; stuck-at faults; truth table enumerating method; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Logic circuits; Logic functions; Logic gates; Logic testing;
Conference_Titel :
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-5650-6
DOI :
10.1109/ISMVL.1994.302188