A Novel Approach to Realistic Worst-case Simulations of CMOS Circuits

To enhance the design of CMOS circuits a new method, named Gradient Analysis, has been proposed and verified. Gradient Analysis enables designers to realistically predict the standard deviation of the circuit performance from measured or guesstimated device parameter variations. It is realistic both in terms of its accuracy and in terms of the number of simulation runs required. With as few as one simulation run the approach is shown to accurately predict the variation of 64K SRAMs Read Access Time and Low Level Output Voltage. Gradient Analysis also provides designers with information on the sensitivity of the circuit performance variations to the device parameter variations.