DocumentCode
1938266
Title
Accelerated verification of RTL assertions based on satisfiability solvers
Author
Fraer, Ranan ; Ikram, Shahid ; Kamhi, Gila ; Leonard, Tim ; Mokkedem, A.
Author_Institution
Logic & Validation Technol., Intel Corp., Haifa, Israel
fYear
2002
fDate
27-29 Oct. 2002
Firstpage
107
Lastpage
110
Abstract
RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check a single property for a given bound, while here we are dealing with hundreds of properties each one requiring a different bound. We propose in this paper a new BMC algorithm that checks multiple properties simultaneously, and yet it is able to detect which properties failed or passed on an individual basis., Moreover, we show that our verification checks are stronger, as they can succeed in proving more properties than the classic algorithm.
Keywords
computability; formal verification; high level synthesis; temporal logic; BMC; Bounded Model Checking; RTL assertion verification; accelerated verification; hardware verification; satisfiability solvers; temporal logic; Acceleration; Algorithm design and analysis; Binary decision diagrams; Context modeling; Electronic design automation and methodology; Formal verification; Hardware; Logic; Usability;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International
Print_ISBN
0-7803-7655-2
Type
conf
DOI
10.1109/HLDVT.2002.1224437
Filename
1224437
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