Title :
Improved testability evaluations in combinational logic networks
Author :
Ercolani, S. ; Favalli, M. ; Damiani, M. ; Olivo, P. ; Riccó, B.
Author_Institution :
DEIS, Bologna Univ., Italy
Abstract :
Two methods for the calculation of fault detection probabilities in combinational networks are presented. These methods provide a better accuracy than existing algorithms and a deeper insight into the effects of first order correlations to multiple fan-out reconvergencies. These techniques have been applied to standard benchmarks as well as to a few commercial circuits and have shown to provide a significant improvement compared with existing methods with minimal drawbacks in terms of required computing resources
Keywords :
automatic testing; combinatorial circuits; fault location; logic testing; calculation of fault detection probabilities; combinational logic networks; commercial circuits; multiple fan-out reconvergencies; required computing resources; standard benchmarks; testability evaluations; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Controllability; Electrical fault detection; Fault detection; Intelligent networks; Logic testing; Observability;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63386
