A vector based backward state justification search for test generation in sequential circuits

An innovative approach to the state justification portion of the sequential circuit automatic test pattern generation (ATPG) process is described. Given the absence of a stored fault, an ATPG controller invokes some combinational circuit test generation procedure, such as the D-algorithm, to identify a circuit state (goal state) and input vectors that will sensitize a selected fault. The state justification phase then finds a transfer sequence to the goal from the present state. A forward fault propagation search can be successfully guided through state space from the present state, but the forward justification search is less efficient and the failure rate is high. This backward-function-level search invokes inverse RTL-level primitives and exploits easy movement of data vectors in structured VLSI circuits. Examples illustrated are in AHPL. This search is equally applicable to an RTL-level subset of VHDL. Combinational logic units are treated as functions, and the circuit states are partitioned into control states and data states. Partial covers, conceptually similar to singular covers in the D-algorithm, model the inverse functions of combinational logic units