Title :
A simple and effective compression scheme for test pins reduction
Author :
Flottes, Marie-Lise ; Poirier, Régis ; Rouzeyre, Bruno
Author_Institution :
Lab. d´´Informatique de Robotique, CNRS, Montpellier, France
Abstract :
We present a simple and effective method for test pin reduction. It must be noticed first that this method is particularly well adapted to the test of SoC since it only deals with test data and does not require any knowledge of the embedded cores. Secondly, it does not induce any delay penalty neither in the circuit itself nor during decompression.
Keywords :
built-in self test; design for testability; embedded systems; formal verification; SoC; compression scheme; embedded cores; test pin reduction; Built-in self-test; Compaction; Encoding; Pins; Robots; System testing;
Conference_Titel :
High-Level Design Validation and Test Workshop, 2002. Seventh IEEE International
Print_ISBN :
0-7803-7655-2
DOI :
10.1109/HLDVT.2002.1224447
