A design method for look-up table type FPGA by pseudo-Kronecker expansion

In FPGA design, interconnections are often more expensive than logic. FPGAs using 3-input lookup tables (LUTs) require many logical levels and complex interconnections. On the other hand, FPGAs using 6-input LUTs require fewer interconnections and fewer logical levels. We show a method to represent logic functions by using pseudo-Kronecker diagrams (PKDD´s). Experimental results show that 2-valued PKDDs require 29% fewer nodes than BDDs, and 4-valued PKDDs require 23% fewer than QDDs, the 4-valued extension of BDDs. Thus, this method is useful for the design of FPGAs with 6-input LUTs. However, when LUTs have less than 6-inputs, this method is not applicable