A novel efficient approach of including frequency-dependent power delivery effects in bus signal integrity simulation

As bus speed targets rise and power supply voltages shrink, the traditionally separate procedures of I/O power delivery design and I/O signaling design must be brought together to comprehend the tight interaction between the two domains. The impact of the frequency-dependent, nonideal behavior of the power delivery system upon the I/O signal integrity and timing must be accurately predicted, rather than loosely guardbanded. This paper describes an efficient way of including these effects in the standard signal integrity and timing bus design process without compromising the speed of simulation