iEDISON: an interactive statistical design tool for MOS VLSI circuits

Author

Yu, T.K. ; Kang, S.M. ; Hajj, I.N. ; Trick, T.N.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

1988

fDate

7-10 Nov. 1988

Firstpage

20

Lastpage

23

Abstract

iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.<>

Keywords

MOS integrated circuits; VLSI; circuit CAD; MOS VLSI circuits; Taguchi method; clock-skew minimization; design optimization; experimental designs; iEDISON; interactive statistical design tool; manufacturing process fluctuations; nonnested experimental design method; regression models; response surface method; statistical performance variations; Circuits; Clocks; Design for experiments; Design optimization; Fluctuations; MOSFETs; Manufacturing processes; Minimization; Response surface methodology; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-0869-2

Type

conf

DOI

10.1109/ICCAD.1988.122454

Filename

122454