Title :
Algebraic division for multilevel logic synthesis of multi-valued logic circuits
Author :
Wang, Hui Min ; Lee, Chung Len ; Chen, Jwu E.
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
Presents the concept of algebraic division for multilevel logic synthesis of multi-valued logic (MVL). At first, an MVL algebraic division procedure is developed based on a basic set of gates. By introducing two MVL Boolean properties: “identical” and “complementary” into the division operation, the procedure is further improved to be a mix-algebraic division procedure, which can obtain more efficient algebraic division to facilitate multilevel logic synthesis of MVL functions. Experimental results show that, in average, the multilevel implementation cost for an MVL function can have 30.1% cost saving over the two-level implementation, and the improved mix-algebraic division procedure can have 19.4% cost saving over the algebraic division procedure
Keywords :
logic design; many-valued logics; Boolean properties; MVL; algebraic division; logic synthesis; mix-algebraic division; multi-valued logic circuits; multilevel logic synthesis; CMOS technology; Circuit synthesis; Cost function; Input variables; Logic circuits; Logic functions; Multivalued logic;
Conference_Titel :
Multiple-Valued Logic, 1994. Proceedings., Twenty-Fourth International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-5650-6
DOI :
10.1109/ISMVL.1994.302221
