Simultaneous optimization of driving buffer and routing switch sizes in an FPGA using an iso-area approach

Author

Chandra, Vikas ; Schmit, Herman

Author_Institution

Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

fYear

2002

fDate

2002

Firstpage

28

Lastpage

33

Abstract

In this paper, we analyze the gain from simultaneous sizing of driving buffers and routing switches on an FPGA interconnect performance. We show that it is not area feasible to build FPGAs with optimally sized interconnects. However, with constrained interconnect area, it is possible to significantly improve the speed of interconnects by simultaneously sizing the driving buffers and routing switches. Our experiments suggest that by simultaneously optimizing the routing resources, delay can be improved by 15-20%. We introduce the idea of iso-area optimization in which we find optimal sizing of routing resources within an overall area constraint. We also show that by making the routing architecture heterogeneous, in terms of routing switch size, we can further improve the performance of an FPGA by 1-12%

Keywords

buffer circuits; circuit optimisation; critical path analysis; delays; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; network routing; FPGA; FPGA interconnect performance; constrained interconnect area; critical path delay; delay improvement; driving buffer optimization; heterogeneous routing architecture; iso-area approach; routing resources optimization; routing switch size optimization; simultaneous sizing; Computer Society; Constraint optimization; Delay; Field programmable gate arrays; Performance analysis; Performance gain; Routing; Switches; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-7695-1486-3

Type

conf

DOI

10.1109/ISVLSI.2002.1016870

Filename

1016870