VLSI implementation for MAC-level DWT architecture

Author

Huang, Shiuh-Rong ; Dung, Lan-Rong

Author_Institution

Dept. of Electr. & Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

92

Lastpage

97

Abstract

This paper presents a VLSI design methodology for the MAC-level DWT processor based on a novel limited-resource scheduling (LRS) algorithm. The r-split Fully-specified Signal Flow Graph (FSFG) of the limited-resource FIR filter has been developed for the scheduling of MAC-level DWT signal processing. Given a set of architecture constraints and DWT parameters, the LRS algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation, and the performance has also been investigated. Because the registers of FIR filtering are reused for the inter-octave storage, the MAC-level DWT architecture may require less extra inter-octave memory than the traditional architecture

Keywords

FIR filters; VLSI; digital signal processing chips; discrete wavelet transforms; integrated circuit design; processor scheduling; signal flow graphs; DWT parameters; FIR filtering registers; MAC-level DWT processor; MAC-level DWT signal processing; VLSI design methodology; architecture constraints; data path; inter-octave memory; inter-octave storage; limited-resource FIR filter; limited-resource scheduling algorithm; multiply/accumulate units; r-split fully-specified signal flow graph; scheduling matrices; Computer architecture; Design methodology; Discrete wavelet transforms; Finite impulse response filter; Flow graphs; Processor scheduling; Registers; Scheduling algorithm; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on

Conference_Location

Pittsburgh, PA

Print_ISBN

0-7695-1486-3

Type

conf

DOI

10.1109/ISVLSI.2002.1016882

Filename

1016882