Field Isolation Using Shallow Trenches for Submicron CMOS Technology

This paper presents a shallow trench isolation technique using plasma etching, LPCVD oxide fill, and planarization. This novel planarization technique applying X-ray lithography and isotropic O2-plasma etch needs no additional mask for block resist patterning over large isolation areas. MOSFETs have been fabricated showing nearly zero channel width loss and no threshold voltage shift down to 0.8 ¿m channel width.