Title :
An efficient partitioning algorithm of combinational CMOS circuits
Author :
Shaer, Bassam ; Dib, Khaled
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Duluth, MN, USA
Abstract :
This paper presents an efficient algorithm to partition combinational CMOS circuits for pseudoexhaustive testing. We present the effect of the partitioning algorithm on critical paths. Our objective is to reduce the delay penalty of test cell insertion for pseudoexhaustive testing. Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to test all of its individual cones. Our testing ensures detection of all nonredundant combinational faults. We have developed an optimization process that can be used to find the optimal size of primary input cone (N) and fanout (F) values, to be used for partitioning a given circuit. In our work, the designer can choose between the fewest number of partitioning points and the least delay in critical path. ISCAS´85 benchmark circuits have been successfully partitioned, and when our results are compared to other partitioning methods, our algorithm makes fewer partitions
Keywords :
CMOS logic circuits; combinational circuits; critical path analysis; fault diagnosis; integrated circuit testing; logic CAD; logic partitioning; logic testing; ISCAS´85 benchmark circuits; combinational CMOS circuits; critical paths; efficient partitioning algorithm; fanout values; nonredundant combinational fault detection; optimization process; primary input cone; pseudoexhaustive testing; test cell insertion delay penalty; CMOS integrated circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Partitioning algorithms; Statistical analysis; Very large scale integration;
Conference_Titel :
VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on
Conference_Location :
Pittsburgh, PA
Print_ISBN :
0-7695-1486-3
DOI :
10.1109/ISVLSI.2002.1016890
