A tabular macromodeling approach to fast timing simulation including parasitics

The approach accounts for RC parasitic loading, overlapping inputs, and incomplete charging or discharging of output nodes. The macromodeling splits the subcircuits data into transistor-gate information and loading information. In a given design many subcircuits have identical gate configurations, but each instance of a gate has a unique RC loading condition. During simulation the gate and loading information is combined and used to calculate output-node voltage changes. All necessary information needed for voltage calculations are precomputed and stored in tables. The proposed macromodeling and the delay method greatly reduce simulation time. The approach has been implemented in a simulator called IDSIM2, and a number of large examples have been simulated. Speedups of up to three orders of magnitude have been obtained compared to standard circuit simulation, with loss of accuracy of less than 10%.<>