DocumentCode
1939881
Title
A practical interconnect driven ASIC design procedure
Author
Chi, Mely Chen ; Tseng, J.M. ; Lee, C.Y. ; Huang, S.H.
Author_Institution
Comput. & Commun. Res. Lab., Ind. Technol. Res. Inst., Chutung, Taiwan
fYear
1998
fDate
13-16 Sep 1998
Firstpage
233
Lastpage
237
Abstract
To shorten design time, it is very important to correctly supply the wire load of nets to the synthesis tool before layout. In this paper, a procedure to create wire load models for a specific processing technology and design flow is presented. Also a physical to logical hierarchy mapping procedure is proposed such that the correct wire load model may be applied to drive synthesis before layout. We apply these methodologies to our company´s products of 0.6 μm technology as illustrations
Keywords
application specific integrated circuits; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; design time reduction; interconnect driven ASIC design procedure; physical to logical hierarchy mapping procedure; synthesis tool; wire load models; Application specific integrated circuits; Capacitance; Communication industry; Computer industry; Delay estimation; Load modeling; Predictive models; Process design; Time to market; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location
Rochester, NY
ISSN
1063-0988
Print_ISBN
0-7803-4980-6
Type
conf
DOI
10.1109/ASIC.1998.722912
Filename
722912
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