Controller and datapath trade-offs in hierarchical RT-level synthesis

We intend to study the impact of control logic on the RT-level design space of a class of digital system. Such an enhancement of the design space is more accurate than several previously reported approaches since control logic has a significant impact on the total cost and performance of the circuit. We present a datapath synthesis framework that is hierarchical in nature; and thus allows the control logic overheads to be factored in hierarchically as well. We introduce hierarchy into the system dynamically by identifying regularity; as such, the proposed method is specific to the signal/image processing domain of application. The impact of control logic is studied with respect to two well known models of FSM´s used in hierarchical systems-the localized model (where each hierarchical sub-unit has its own controller) and the centralized model (where the FSM´s are all centrally located). We demonstrate how regularity facilitates such a study through the use of realistic area-delay estimators that lead us to better understanding of the RT design space