DocumentCode
1940130
Title
Specification of interface components for synchronous data paths
Author
Gutberlet, P. ; Rosenstiel, W.
Author_Institution
Forschungszentrum Inf., Karlsruhe Univ., Germany
fYear
1994
fDate
18-20 May 1994
Firstpage
134
Lastpage
139
Abstract
The simulation semantics of VHDL necessitates the specification of the interface signal transitions at bit level with exact timing which is not well suited for abstract specification and synthesis. The paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the transformations to generate a RT data path while holding the exact simulation semantics at the interface
Keywords
circuit analysis computing; digital simulation; formal specification; specification languages; RT data path; VHDL; abstract specification; abstraction levels; behavioural description; exact simulation semantics; exact timing; high level synthesis; interface components; interface signal transitions; simulation semantics; synchronous data paths; Circuit synthesis; Clocks; Delay; High level synthesis; Petri nets; Protocols; Signal processing; Signal synthesis; Specification languages; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on
Conference_Location
Niagara-on-the-Lake, Ont.
Print_ISBN
0-8186-5785-5
Type
conf
DOI
10.1109/ISHLS.1994.302330
Filename
302330
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