Title :
Specification of interface components for synchronous data paths
Author :
Gutberlet, P. ; Rosenstiel, W.
Author_Institution :
Forschungszentrum Inf., Karlsruhe Univ., Germany
Abstract :
The simulation semantics of VHDL necessitates the specification of the interface signal transitions at bit level with exact timing which is not well suited for abstract specification and synthesis. The paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction levels are separated. It shows the transformations to generate a RT data path while holding the exact simulation semantics at the interface
Keywords :
circuit analysis computing; digital simulation; formal specification; specification languages; RT data path; VHDL; abstract specification; abstraction levels; behavioural description; exact simulation semantics; exact timing; high level synthesis; interface components; interface signal transitions; simulation semantics; synchronous data paths; Circuit synthesis; Clocks; Delay; High level synthesis; Petri nets; Protocols; Signal processing; Signal synthesis; Specification languages; Timing;
Conference_Titel :
High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on
Conference_Location :
Niagara-on-the-Lake, Ont.
Print_ISBN :
0-8186-5785-5
DOI :
10.1109/ISHLS.1994.302330
