Title :
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs
Author :
Chen, Chih-Tung ; Parker, Alice C.
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
We present an efficient and effective approach for checking synthesized RTL designs. This approach uses a hybrid numeric/symbolic simulation to extract the functional behavior of a design while taking into account the interaction between the data and control paths as well as the clocking scheme and delays, and employs a graph-comparison procedure to perform the checking task. The value of this work was shown by its ability to identify problems with an early version of the ADAM Control Signal Generator (CSG) software, which was then corrected accordingly
Keywords :
circuit analysis computing; digital integrated circuits; formal verification; integrated logic circuits; logic CAD; time measurement; ADAM Control Signal Generator; RTL designs; clocking scheme; control paths; data paths; delays; formal verification; functional behavior; functional compatibility; graph-comparison procedure; hybrid numeric/symbolic program; synthesized designs; timing compatibility; Automatic control; Clocks; Control system synthesis; Control systems; Costs; Delay; Error correction; High level synthesis; Numerical simulation; Timing;
Conference_Titel :
High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on
Conference_Location :
Niagara-on-the-Lake, Ont.
Print_ISBN :
0-8186-5785-5
DOI :
10.1109/ISHLS.1994.302333
