DocumentCode
1940202
Title
Concurrent testing in high level synthesis
Author
Singh, Ravibala ; Knight, John
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear
1994
fDate
18-20 May 1994
Firstpage
96
Lastpage
103
Abstract
For digital circuits synthesized from data-flow graphs, this paper presents a method to test the circuit concurrently with its normal operation. The method tests hardware elements when they are not in use in the data-flow graph. An algorithm for synthesizing the test circuit is presented that starts with the data-flow graph, generating a circuit to cycle test vectors through the idle hardware and produce a signature so as to give a built-in-self-test. By utilizing idle computational time for testing, the method reduces test-time overheads
Keywords
built-in self test; digital integrated circuits; integrated circuit testing; logic testing; parallel processing; built-in-self-test; concurrent testing; data-flow graphs; digital circuits; high level synthesis; idle computational time; test-time overheads; Built-in self-test; Centralized control; Circuit faults; Circuit synthesis; Circuit testing; Control systems; Data processing; Electronic equipment testing; High level synthesis; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on
Conference_Location
Niagara-on-the-Lake, Ont.
Print_ISBN
0-8186-5785-5
Type
conf
DOI
10.1109/ISHLS.1994.302335
Filename
302335
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