An integrated approach to retargetable code generation

Author

Wilson, Tom ; Grewal, Gary ; Halley, Ben ; Banerji, Dilip

Author_Institution

VLSI-CAD Group, Guelph Univ., Ont., Canada

fYear

1994

fDate

18-20 May 1994

Firstpage

70

Lastpage

75

Abstract

Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified and jointly optimized within a single integer linear programming (ILP) model. ILP modeling provides a powerful methodology for generating high-quality code for a variety of ISPs

Keywords

automatic programming; instruction sets; integer programming; linear programming; parallel programming; program compilers; software portability; special purpose computers; code generation; compilers; high-quality code generation; instruction level parallelism; integer linear programming model; retargetable code generation; special-purpose instruction set processors; specialized register capabilities; Chip scale packaging; Counting circuits; Design optimization; Digital signal processing chips; Hardware; Optimizing compilers; Prototypes; Registers; Service oriented architecture; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

High-Level Synthesis, 1994., Proceedings of the Seventh International Symposium on

Conference_Location

Niagara-on-the-Lake, Ont.

Print_ISBN

0-8186-5785-5

Type

conf

DOI

10.1109/ISHLS.1994.302339

Filename

302339