Design of the CIC decimation filter based on SOPC Builder

Author

Song, Wenmiao ; Liu, Bo

Author_Institution

Dept. of Electron. & Commun. Eng., North China Electr. Power Univ., Baoding, China

Volume

9

fYear

2010

fDate

9-11 July 2010

Firstpage

602

Lastpage

605

Abstract

This CIC (Cascaded integrator comb) decimation filter is widely applicable to reduce the data sampling rate in DDC (Digital Down Conversion). In this paper, the theory of CIC decimation filter architecture is researched. Based on the idea of software defined radio (SDR), we go forwards a new method to design CIC decimation filter. This method makes use of SOPC (System On Programmer Chip) technology. We use the tool of SOPC Builder to design the CIC decimation filter IP core. Then we design other relevant IP core resources and build a SOPC system. Finally the designed system is downloaded to the SOPC comprehensive experiment testbed. Experimental results show that the designed CIC decimation filter component can be implemented successfully based on FPGA, and the functions of CIC decimation filter component are programmable, reliable and portable.

Keywords

comb filters; data conversion; field programmable gate arrays; integrated circuit design; system-on-chip; CIC decimation filter design; FPGA; SOPC builder; cascaded integrator comb decimation filter; data sampling rate; digital down conversion; software defined radio; system on programmer chip; Light emitting diodes; FPGA; IP Core; SOPC; cascaded integrator comb decimation filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-5537-9

Type

conf

DOI

10.1109/ICCSIT.2010.5564142

Filename

5564142