Assembly-stress-mechanism in pad areas of flip chip package on high-k/metal gate transistors

We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in μm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in μm pitch. In this structure, the downward stress increases the ids of these Trs. The causes of assembly stress in pad areas are: 1) Local stress concentration to the Under Bump Metal (UBM) step at the Polyimide film (PI) aperture edge, which is induced by the contraction of the PI, 2) Global stress to the solder bump, which is induced by the contraction of the Underfill resin (UF). These stresses have temperature dependence, and are relaxed between the UBM formation temperature and the glass-transition temperature (Tg) of the UF. Based on the mechanism, we propose a new structure without step in the UBM, and expect to reduce assembly stress by 30% with the new structure.