Reliability analysis of NAND gates with modified channel length in series n-MOSFETs

A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented in standard 90 nm CMOS process. Stress time t_strs dependence of degradation ratio of delay time t_d and operation current I_OP follow a power law of t_strs. A channel length modification from 0.10 to 0.11 μm for the topmost n-MOSFET in series connected MOSFETs of NAND gates provides not only leakage current reduction but reliability improvement with less performance degradation under high voltage stress condition.