A submicron MOSFET model for simulation of analog circuits

An efficient MOSFET model for accurate prediction of the drain current and the drain conductance of a short-channel MOSFET is presented. Earlier models for channel length modulation are not suitable for simulating analog circuits for which the drain conductance is important. Empirical expressions derived from measured I-V characteristics are used to fit well the behavior of drain conductance with gate and substrate bias predicted by the model, which thus overcomes the limitations of earlier models. The model was implemented in SPICE, and several simple circuits have been tested without encountering any convergence problems.<>