Laterally etched undercut (LEU) technique to reduce base-collector capacitances in heterojunction bipolar transistors

Author

Liu, W. ; Hill, D. ; Hin-Fai Chau ; Sweder, J. ; Nagle, T. ; Delaney, J.

Author_Institution

Corp. R&D, Texas Instrum. Inc., Dallas, TX, USA

fYear

1995

fDate

Oct. 29 1995-Nov. 1 1995

Firstpage

167

Lastpage

170

Abstract

We report a novel fabrication process aimed at reducing the parasitic junction capacitance of AlGaAs-GaAs heterojunction bipolar transistors. The process, named as the Laterally Etched Undercut (LEU) process, physically removes the extrinsic base-collector junction area and results in a cantilever structure. The DC, small-signal, and large-signal performances of the LEU devices are compared to those obtained from the conventional devices.

Keywords

III-V semiconductors; aluminium compounds; capacitance; etching; gallium arsenide; heterojunction bipolar transistors; semiconductor technology; AlGaAs-GaAs; DC performance; GaAs; HBT fabrication process; LEU process; base-collector capacitance reduction; cantilever structure; extrinsic base-collector junction area; heterojunction bipolar transistors; large-signal performance; laterally etched undercut technique; parasitic junction capacitance; small-signal performance; Bismuth; Fabrication; Gallium arsenide; Heterojunction bipolar transistors; Instruments; Microwave devices; Parasitic capacitance; Power amplifiers; Power generation; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1995. Technical Digest 1995., 17th Annual IEEE

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-2966-X

Type

conf

DOI

10.1109/GAAS.1995.528986

Filename

528986