Statistical Defectivity Control for VLSI Devices

A method used in designing test chips for defect monitorinig of VLSI processes is presented. The purpose of the method is to maximize the accuracy of defect density estimations. This is achieved by appropriate sizing of test chip structures. The optimal dimension of test structure is computed using a model relating the confidence interval for the defect density D with the sample size and test structure dimension. The Poisson and negative binomial yield models are used in the calculation. The application to real life VLSI processes is outlined.