DocumentCode
1942208
Title
A photocell-array with on-chip normalisation and mismatch compensation
Author
Fikos, G. ; Voliotidis, C. ; Siskos, S.
Author_Institution
Aristotelian Univ. of Thessaloniki, Greece
Volume
1
fYear
2003
fDate
1-4 July 2003
Firstpage
621
Abstract
In this paper, a photosensitive array consisting of a novel cell is proposed. The main features of the array are: i) logarithmic conversion of photocurrent to voltage, ii) normalization of each pixel´s photocurrent towards the average photocurrent, iii) correction of pixels mismatches compensating for fabrication mismatch and iv) flexible interfacing with other circuitry. A 16×16 prototype array of the proposed cells, along with the corresponding 8-bit decoder have been designed and fabricated through the AMS 0.6μ standard CMOS process, and the validity of the above features has been verified through experimental results. The array can be used as a core unit of an image recognition system.
Keywords
CMOS integrated circuits; VLSI; decoding; image coding; image recognition; integrated optoelectronics; photoelectric cells; 0.6 micron; 8 bit; 8-bit decoder; AMS; image recognition system; logarithmic conversion; mismatch compensation; photocurrent; photosensitive array; standard CMOS process; Circuits; Decoding; Fabrication; Image recognition; Layout; Lighting; Photoconductivity; Prototypes; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and Its Applications, 2003. Proceedings. Seventh International Symposium on
Print_ISBN
0-7803-7946-2
Type
conf
DOI
10.1109/ISSPA.2003.1224780
Filename
1224780
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