Combined C-V/I-V front-end-of-line measurement

Author

Polonsky, Stas ; Realov, Simeon ; Liao, Jiun-Hsin ; Hargrove, Michael ; Ketchen, Mark

Author_Institution

IBM Res. T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2012

fDate

19-22 March 2012

Firstpage

241

Lastpage

244

Abstract

We present a simple test structure to measure C-V and I-V curves of the same nominal size FET. The structure is simple enough to be used for technology development, requires only first metal for routing, and allows parallel test. It is an extension of FEOL QVCM technique, reported at this conference in 2011, and uses dc current measurement for C-V extraction with atto-Farad resolution. The utility of the presented technique is illustrated with 22 nm SOI device characterization.

Keywords

electric current measurement; elemental semiconductors; field effect transistors; semiconductor device testing; silicon; silicon-on-insulator; C-V extraction; C-V-I-V front-end-of-line measurement; DC current measurement; FEOL QVCM technique; SOI device characterization; Si; atto-Farad resolution; metal; nominal-size FET; parallel test; routing; size 22 nm; technology development; test structure; Capacitance-voltage characteristics; Clocks; Force measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2012 IEEE International Conference on

Conference_Location

San Diego, CA

ISSN

1071-9032

Print_ISBN

978-1-4673-1027-7

Type

conf

DOI

10.1109/ICMTS.2012.6190656

Filename

6190656

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1942364