Title :
A new algorithm for CMOS gate matrix layout
Author :
Chen, C.Y.R. ; Hou, C.Y.
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
Abstract :
Efficient algorithms for CMOS gate matrix layouts which have fully utilized the duality between NMOS and PMOS are presented. Improper assumptions made by previous authors are pointed out. Problems which have prevented previous algorithms from reaching a real optimal result are discussed and solved. Significant improvements are achieved over previous algorithms.<>
Keywords :
CMOS integrated circuits; circuit layout CAD; CMOS gate matrix layout; NMOS/PMOS duality; algorithms; optimal result; Circuits; MOS devices; Minimization; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122480
