Channel Engineering using RP-CVD Epitaxy for High Performance CMOS Transistors

Channel engineering is of central importance for optimizing the electrical behaviour of deep sub-¿m transistors. CVD-epitaxy at relatively low temperatures provides very sharp doping profiles in both n- and p-channel devices, with doping concentrations in the range of 10¹⁶ to 5-10¹⁸ cm^¿3. Boron and arsenic are used as dopants. The thermal process budget has been minimized using 5nm gate oxides grown at 700°C or 800°C, and RTP annealing. N-surface- and p-buried-channel transistors with 300nm effective channel length have been fabricated, with saturation currents up to 500¿A and 180¿A, respectively, at a power supply voltage of 2.5V.